The fabrication of integrated circuitry may involve formation of electrically conductive lines across a semiconductor substrate. A damascene process may be utilized to form such lines. FIGS. 1-3 illustrate an example prior art damascene process.
Referring to FIG. 1, a semiconductor construction 10 comprises a base 12, and an electrically insulative material 14 formed over the base. The base may comprise monocrystalline silicon. The insulative material 14 may comprise, for example, one or more of silicon dioxide, silicon nitride, and any of various doped silicon oxides (for instance, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), etc.). The insulative material 14 may be homogeneous, as shown, or may comprise multiple materials in discrete layers.
A plurality of openings 16-18 are formed to extend into material 14. The openings may be formed by utilizing a patterned photoresist mask (not shown) to define locations of the openings, utilizing one or more etches to extend the openings into such locations, and then removing the photoresist mask to leave the structure shown in FIG. 1.
Referring to FIG. 2, materials 20 and 22 are provided within the openings to line the openings, and then the lined openings are filled with copper 24.
The material 20 may comprise titanium nitride, tantalum nitride, tantalum/ruthenium, tantalum, or titanium oxide, and may function as a barrier to block copper diffusion.
The material 22 may, for example, comprise ruthenium and nitrogen, or as another example may consist of ruthenium. The material 22 may be utilized as a stratum to adhere the subsequently deposited copper 24.
Referring to FIG. 3, construction 10 is subjected to a polishing process (for instance, chemical-mechanical polishing) to form a plurality of electrically isolated conductive lines 25-27 from the materials 20, 22 and 24 within the openings 16-18.
The conductive lines 25-27 shown in FIG. 3 are idealized, in that the copper 24 completely and substantially uniformly fills each of the openings 16-18. In practice, difficulties may be encountered in attempting to substantially uniformly fill the openings with the copper; particularly as the openings become increasingly narrow with higher levels of integration.
FIG. 4 illustrates a problem that may occur during the formation of copper 24 within the openings 16-18. Specifically, the copper is not uniformly deposited within the openings, and accordingly voids 28 are formed in some of the openings. The voids may be of different sizes, as shown, and accordingly the conductivity of various conductive lines ultimately formed within the openings will vary from one line to another. Such non-uniformity of conductivity may impair, or destroy, the operability and/or reliability of an integrated circuit comprising such conductive lines. Accordingly, it is desired to develop improved methods for fabrication of electrically conductive lines.